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    • 专利摘要:
    The present invention relates to a ROM embedded in a multilayer integrated circuit including rows of transistor memory cells. To reduce the area, each transistor in a row shares a terminal with an adjacent transistor in the row. By doing so, adjacent transistors share either a source or a drain. Each contact line of the plurality of contact lines is connected to a respective common terminal and serves as an address terminal for the cell. The plurality of metal layers are connected to the other of the drain or source terminals by fill vias and have a final metal layer that defines a metal pad for the other terminals. Fill vias connect the selected metal pad to the selected signal line to provide an output " 1 " from the selected cells. Signal lines not connected to the metal pads by the fill vias provide an output "0" from the selected cells.
    公开号:KR20020097486A
    申请号:KR1020027015627
    申请日:2001-04-11
    公开日:2002-12-31
    发明作者:패리스패트리스；모톤브루스엘；시오섹월터제이；오로라마크；스미스로버트
    申请人:모토로라 인코포레이티드；
    IPC主号:
    专利说明:

    Ultra-late programming ROM and method of manufacture}
    [2] Most, but not all, embedded microcontroller components have on-board read-only memory (ROM) modules. During technology development, system designers commonly use built-in nonvolatile memory (NVM) to debug microcontroller code. However, once the system and code are distributed to users and mass production begins, they use ROM to replace nonvolatile memory. This can directly reduce die size (program ROM is a major factor in determining die size) and indirectly reduce test costs by reducing costs.
    [3] Increasingly, consumers recognize that much of the value they add to microcontroller systems will be intellectual property (eg, software, algorithms, etc.) made from the code that runs the microcontroller system. Thus, suppliers need to make the same die in all other respects (CPU, digital modules, analog modules, I / O, etc.), while varying the code stored in the ROM. For maximum flexibility of the production line, it is desirable for the producer to be able to delay installing the code in the ROM during the manufacturing process as much as possible. A general inventory of wafers outside the ROM coding perspective does not meet every user's needs.
    [4] Another reason for delaying code installation in ROM is that users sometimes want to upgrade their code and algorithms. When such code changes and corrections are made, the consumer finds a minimum cycle time. The earlier the code is stored in ROM, the longer the cycle time for the code update.
    [5] Because of this pressure, producers have devised means to delay ROM programming later in the manufacturing process. Although programmed ROM is still in use in active area formation (US Pat. Nos. 4,021,781, 4,151,020, 4,208,726), late-programmed ROMs are becoming increasingly popular. The latter ROM programming means is achieved by ion implantation prior to the deposition of ILD0 (first interlevel dielectric layer). Examples are disclosed in US Pat. Nos. 4,230,505, 4,342,100, 4,390,971, 5,585,297. In some cases, high energy injection or electron beam (US Pat. No. 4,272,303, 4,591,891), metal as a mask (US Pat. No. 4,384,399), or etch-back implantation through ILD0 regions (US Pat. No. 5,514,609) As a result, data programming to the ROM is delayed later in the process. Programming is also delayed until a contact is made (US Pat. Nos. 4,326,329, 4,219,836, 5,484,842, 5,471,416). Here, the ROM is programmed using the gate contacts of the transistors in the array. Some ROMs that delay programming later will result in larger bit cell sizes.
    [6] Modern processes for high performance applications have five metal layers. A large number of tie layers tend to be used in conjunction with planarization techniques such as chemical mechanical polishing (CMP). The longer back-end cycle time means that ROM programming in a step adjacent to ILD0 deposition is no longer in the second half of the process. In order to keep cycle time variations for customer ROM code low, ROM programming must be moved later in the process. In addition, the bit cell size should be kept small and reduced if possible.
    [1] FIELD OF THE INVENTION The present invention generally relates to read-only memory (ROM), and more particularly, to a ROM that can be programmed later in the manufacturing process and a method of manufacturing the same.
    [8] 1 is a plan view showing a portion of a ROM array in accordance with an embodiment of the present invention.
    [9] FIG. 2 is a cross-sectional view showing a part of the ROM arrangement cut along the line 2-2 of FIG. 1; FIG.
    [10] 3 is a cross-sectional view showing a part of the ROM arrangement cut along line 3-3 of FIG.
    [11] 4 is a plan view showing a portion of a ROM array according to another embodiment of the present invention.
    [12] FIG. 5 is a cross-sectional view showing a portion of the ROM arrangement cut along line 5-5 of FIG. 4; FIG.
    [13] FIG. 6 is a cross-sectional view of a portion of the ROM array cut along line 6-6 of FIG. 4; FIG.
    [14] 7 is a plan view showing a portion of a ROM array according to another embodiment of the present invention.
    [15] FIG. 8 is a sectional view of a portion of the ROM arrangement cut along the 8-8 line in FIG. 7; FIG.
    [16] FIG. 9 is a cross-sectional view of a portion of the ROM array taken along line 9-9 of FIG. 7; FIG.
    [17] FIG. 10 is a cross-sectional view illustrating a portion of a ROM array cut along line 10-10 of FIG. 7. FIG.
    [18] FIG. 11 is a cross-sectional view of a portion of the ROM array cut along line 11-11 of FIG. 7; FIG.
    [19] 12 is a plan view showing a portion of a ROM array according to another embodiment of the present invention.
    [7] Therefore, it is highly desirable to provide a method and structure that is capable of overcoming these problems and which is economical and easy to implement, install and use. In addition, in some specific applications, the chip region has a substantially reduced structure.
    [20] As described in detail below, the present invention relates to a ROM arrangement implemented as part of a ROM, such as a processor, or part of an integrated circuit, such as a ROM as a finished product. Such a ROM has a semiconductor substrate on which a plurality of switching transistors are formed, each switching transistor being logically and geometrically arranged in an array having first and second dimensions, the switching transistor having the function of a memory cell.
    [21] Each memory cell has a control terminal such as a gate or base terminal and a first and second controlled terminal such as a drain and a source or an emitter and a controller. In an embodiment, one of the control terminal and the controlled terminal acts as an address line or signal line for the memory cell to provide means for selectively enabling a given memory cell.
    [22] The second controlled terminal, drain or collector, is selectively connected to one or more evaluation or read or bit lines by fill vias, preferably, each memory cell is connected to the first and second evaluation lines so that each memory cell is evaluated. Encode a plurality of states corresponding to a line. For various reasons, this condition generally consists of one state on the zero evaluation line connected to the controlled terminal and one state on each of the evaluation lines connected to the controlled terminal.
    [23] Also, the ROM preferably comprises two or more conductive connection layers having a first or early or sublayer comprising one or two address lines. Preferably, these address lines are arranged along a first logical or column region of the array in which each cell in the column shares the same address line.
    [24] The second conductive layer comprises one or preferably first and second evaluation lines. Preferably, they are arranged along a second logic or row area of the array with each memory cell in a row sharing the same evaluation line. This allows the ROM manufacturing process at the end of the process to determine ROM programming by providing and filling selected vias at the end of the process. The ROM may comprise third, fourth and more evaluation lines, each evaluation line being selectively connected to a second controlled terminal, where such additional evaluation line is selectively connected to the early or second conductive layer. Can be formed. With the first, second and third evaluation lines, the memory cell can encode a plurality of bits corresponding to four state memory cells, which are particularly suitable for encoding two bits per cell. Each of these concepts will be described in more detail in connection with the drawings for each embodiment of the present invention.
    [25] 1 is a plan view of a ROM according to an embodiment of the present invention. ROM 10 is preferably implemented as a multilayer integrated circuit as an integral part of a circuit according to standard fabrication techniques. In FIG. 2, which is a cross-sectional view taken along line 2-2 of FIG. 1, the ROM 10 includes a plurality of (seven in FIG. 2) switching transistors 12, 13, 14, 15, 16, 17, and 18. The semiconductor substrate 11 is included. The switching transistors 12, 13, 14, 15, 16, 17, 18 are only part of a single row of transistor arrays and have four rows shown in the top view of FIG. Likewise, transistors 12, 70, 71, 72 are part of one column of the transistor array having seven columns shown in FIG. As described in detail below, each transistor comprises a memory cell defining a column (part) of the memory cell and a transistor 12, 13 defining a row (or part of a row) of the transistors 12, 70, 71, 7 2. , 14, 15, 16, 17, 18). In this embodiment, it is apparent to those skilled in the art that an NMOS transistor is used but other conductive or other types of transistors are available. The portion of ROM 10 cut along line 2-2 has been described as part of the memory cell, and the portion of ROM 10 cut along line 3-3 has been described as part of the rows of memory cells, but this is by definition. It must be understood. That is, the portion of ROM 10 cut along line 2-2 may be described as part of a column of memory cells, and the portion of ROM 10 cut along line 3-3 may be described as part of a row of memory cells. Can be.
    [26] Transistors 12, 13, 14, 15, 16, 17, 18, 70, 71, 72 can be manufactured using convenient techniques. For example, in an embodiment, an oxide gate layer is formed on the surface of the substrate 11, and the gates 20, 21, 22, 23, 24, 25, 26 are formed using common patterning techniques. Control terminals or gates 20, 21, 22, 23, 24, 25, 26 are, for example, polysilicon doped to enhance conductivity. Further, each gate 20, 21, 22, 23, 24, 25, 26 extends at right angles in FIG. 2 for the length of the transistor array or subarray such that the transistors of the array or subarray are arranged in columns. Formed into long strips of conductive material. Drains 27, 28, 29, 30 and sources 31, 32, 33, 34 are formed using standard self-aligned implantation techniques.
    [27] Here, the controlled terminals or drains 27, 28, 29, 30, and the other controlled terminals or sources 31, 32, 33, 34 are alternated along the rows of FIG. 2, so that each transistor in the row (eg, Transistors 12, 13, 14, 15, 16, 17, 18) share terminals with adjacent transistors in a row. For example, the first adjacent pair of transistors 12, 13 in a row share a source terminal 31, and the second adjacent pair of transistors 13, 14 in a row share a drain electrode 28. Thus, the first pair of adjacent transistors 12/13, 14/15, 16/17 in each row share the source terminal and the other pair of adjacent transistors 13/14, 15/16, 17/18 in the row. ) Share the drain terminal.
    [28] The shared terminal concept is optional and included in this embodiment to further reduce the memory area. However, if the substrate area is not a problem, individual transistors may be manufactured rather than transistors sharing terminals. In this embodiment where a MOS memory cell or transistor is used, each terminal referred to as a source or a drain is arbitrary and the transistor is symmetrical in operation. For this reason, these terminals are often referred to as source / drain and are referred to as controlled terminals in the present invention. In the operation of an NMOS transistor, a source generally refers to a terminal connected to the lower potential of two terminals, or a terminal through which current flows when the cell or transistor is enabled or turned on and the drain is connected to both potentials.
    [29] Each drain terminal 27, 28, 29, 30 is connected to a first signal line, which in this embodiment is referred to as a " pre-charge " line. Charge ”and not in other modes. In general, during operation, a“ precharge ”line is connected to a common potential, such as ground, to complete the circuit through each of the transistors or memory cells. In the embodiment shown in Fig. 3, " precharge " lines 36, 37, 38, 39 are formed in the first metal layer and extend at right angles in Fig. 2 extending parallel to each column of transistors in the array (Fig. 1). Each drain of each transistor is connected to an adjacent one of the " precharge " lines 36, 37, 38, 39 by contact 40. Transistors formed by transistors 12, 70, 71, 72 A portion of the columns of poly form the gate 20 for each transistor And share a common strip of conductive material, such as licon or metal, and likewise share a common “precharge” or first signal line 36. Here, once a transistor array is formed, the entire array is an insulating material (eg : Silicon oxide), then (optionally planarized), and then patterned to form an opening for contact 40 (and other contacts to be described), which opens contact 40 (optionally another contact). The first metal layer is a metal, polysilicon, etc. The first metal layer is deposited (if it is metal) to contact (40). 41) and " precharge " lines 36, 37, 38, 39 and form contact or connection lines included in the first metal layer.
    [30] In addition to the contacts 40 connecting the " precharge " lines 36, 37, 38, and 39 to the drains 27, 28, 29, and 30, respectively, the contacts 41 in the first metal layer are formed of a source 31, 32, 33 and 34 are electrically connected to line 42. Depending on the particular integrated circuit in which the ROM 10 is embedded (the number "n" of metal layers in the IC), the plurality of "n-1" layers are also shared with each other by conductive vias filled with an electrically conductive material. Is connected to the source terminals 31, 32, 33, 34; Therefore, the vias are referred to as filled vias. Since the conductive layer is mostly formed of a metal, it will be referred to as a metal layer in the present invention and other conductive materials (such as doped semiconductor materials) may be used in some specific applications.
    [31] In cross-sectional view taken along line 3-3 of FIG. 3, the plurality of conductive pads 45, 46, 47, 48 of the transistors 12, 70, 71, 72 for each of the shared source terminals 31 are provided in plurality. It can be seen that the metal layer is formed on the final metal layer (metal layer n-1). Conductive pads 45, 46, 47, 48 are generally rectangular in shape and have long axes that intersect or planar in FIG. 3 to reduce chip area.
    [32] The plurality of read or evaluate lines or the second signal lines 50, 51, 52, 53, 54, 55, 56 are formed from metal layer n and are formed by conductive pads (vias 60) selectively filled with an electrically conductive material. 45,46,47,48); Therefore, filled vias are called filled vias. As best shown in FIG. 1, evaluation lines 50, 51, 52, 53, 54, 55, 56 generally extend parallel to a transistor row with two evaluation lines connected to each row of transistors in the transistor array. do. For example, in particular in FIGS. 1, 3, evaluation lines 50, 51 are connected to transistor rows including transistors 12, 13, 14, 15, not shown in FIG. 1 or 3, and evaluation lines ( It can be seen that 52 and 53 are connected to the subsequent transistor row including transistor 70 and that evaluation lines 54 and 55 are connected to the subsequent transistor row including transistor 71. Fill via 60 connects a pad selected from conductive pads to a selected one of a plurality of evaluation lines to define a first logical output of a row of memory cells. In FIG. 1, in the first row of transistors, the fill via 60 connects a pad selected from the conductive pads 45 to a line selected from the plurality of evaluation lines 50 and 51. For example, only evaluation line 50 is connected to conductive pad 45, and evaluation lines 52 and 53 are connected to conductive pad 46. Further, evaluation lines 50 and 51 are both connected to the second conductive pads in the first row of transistors, and only evaluation line 52 is connected to the second conductive pads in the second row of transistors.
    [33] In order to read the information stored in the ROM 10 (ignoring addressing or other connections contained in the plurality of metal layers 1 to n-1), individual memory cells in the array can be addressed by activating the transistors that make up the cell. Can be. Taking transistor 12 as an example, addressing is achieved by connecting " precharge " line 36 to a common potential, such as ground, and providing the appropriate potential to gate 20. By applying an appropriate potential to the evaluation line 50 and measuring the current flow, the presence of the filling via 60 between the conductive pad 45 and the evaluation line 50 is determined. In this example, current flows because the fill via 60 is present. That is, the vias connecting the evaluation line 50 to the source 31 are filled with an electrically conductive material. Similarly, transistor 70 is properly biased with first signal line or " precharge " line 36 and gate 20 and is addressed using second signal line or evaluation line 52,53. In this case, the fill via 60 connects the evaluation line to the conductive pad 46, so that current flows for each evaluation line.
    [34] Transistor 13 is addressed by connecting " precharge " line 37 to a common potential, such as ground, and providing the appropriate potential to gate 21. By applying an appropriate potential to the evaluation line 51 and measuring the current flow, the presence of the filling via 60 between the conductive pad 45 and the evaluation line 51 is determined. In this example, no fill via 60 is present, so no current flows (see FIGS. 1 and 3). That is, the vias connecting the evaluation line 51 to the source 31 are not filled with an electrically conductive material.
    [35] Transistor 14 is addressed by connecting " precharge " line 37 to a common potential, such as ground, and supplying the appropriate potential to gate 22, and evaluating evaluation lines 50, 51 as described above. It is read by connecting. Transistor 15 is addressed by connecting " precharge " line 38 and the appropriate potential to gate 23, and is read by connecting evaluation lines 50 and 51 as described above. Transistors 14 and 15 have fill vias 60 connected to the transistors so that current can flow for both evaluation lines when performing a read operation. In a similar manner, each cell of the array is read. In this embodiment, the current flow, or the presence of fill via 60, is designated as logic " 1 ", and the absence of fill via 60 or lack of current flow is designated as logic " 0 ". As will be apparent to those skilled in the art, certain logic outputs may be reversed depending on the accompanying equipment.
    [36] 4 illustrates a ROM 110 in accordance with another embodiment of the present invention. In the present embodiment, components similar to those of Figs. 1 to 3 are given the same numbers, and a 1 is added to indicate that the other embodiment. In general, ROM 110 is similar to ROM 10, with only a plurality of " precharge " lines 136, 137, 138, 139 formed on substrate 111 as an extension of drain terminals 127, 128, 129, 130, for example. For example, instead of doping only individual drain terminals, doping the entire line (or by including polysilicon or other semiconductor material on the surface of the substrate 111). In any case, the “precharge” lines 136, 137, 138, and 139 extend at right angles in the cross section taken along line 5-5 of FIG. 5. In this embodiment, the "precharge" lines are only contacted at the edge of the array or block. As shown in FIG. 4, the gate line and the transistor are moved adjacently, which results in a reduction in the area of the ROM 110. However, due to the high resistance generated by the semiconductive " precharge " line, the performance of the ROM 110 is reduced compared to the ROM 10, but can be reinforced by strapping or the like.
    [37] In ROM 10 or ROM 110, all of the connection layers through metal layer n-1 are completed before programming. At a convenient time after the metal layer n-1 is completed, the insulating layer is deposited on the metal layer n-1 and planarized. Note that the planarization step is optional. Fill vias 60 or 160 connected to the conductive pads are formed using a mask containing desired programming information (ie, the presence of fill vias 60 or 160). Here, depending on the manufacturing technique used, the fill vias 60, 160 may be formed as part of the metal layers n-1, n or of other materials with little change in process. After formation of fill vias 60 or 160, final metal layer n is deposited and etched, and an inert layer is deposited and etched to complete the ROM.
    [38] As described above, the ROM 10 or ROM 110 is programmed with specific information after the entire ROM is manufactured. Therefore, since the process takes place after the connection layer is completed, the increase in the connection layer has little effect on the delay of programming. In addition, the ROMs are identical in all respects up to the programming stage, so the latter cycle time for a particular code is substantially reduced. In addition, the bit cell size is kept small and may be reduced in some applications. Therefore, the user code can be changed in the last few minutes of time without substantially changing the cycle time.
    [39] One way to read ROM 10 or ROM 110 is as follows:
    [40] A. Assign all "precharge" lines to V D, Read ;
    [41] B. decode the address of the byte / block to be readable;
    [42] C. Assign the selected gate electrode or electrodes to V G, Read ;
    [43] D. detect appropriate evaluation lines using any means;
    [44] In this method, the evaluation line of the cell with missing fill vias 60 or 160 is not connected to the "precharge" line and is not located at V D, Read . These cells are distinguished from the evaluation line of the cell with the original fill vias. Therefore, the method can distinguish two bit states.
    [45] Another way to read ROM 10 or ROM 110 is as follows:
    [46] A. Assign an evaluation line to V D, Read for the data to be read;
    [47] B. Assign the "Precharge" line to V G, Read ;
    [48] C. decode the address of the data into the row;
    [49] D. detect appropriate evaluation lines using any means;
    [50] Through the above process, the "precharge" line of the cell with missing fill vias is not connected to the evaluation line, and current flows in the corresponding evaluation line.
    [51] 7 is a plan view of another embodiment of a ROM 210 in accordance with the present invention. In this embodiment, components similar to those in FIGS. 1-3 and 4-6 are used and ROM 210 operates in a similar manner. Therefore, the following description will focus on the differences and the description of FIGS. 7-12 is minimized. In general, ROM 210 has a configuration similar to ROM 10, except that additional evaluation lines are included in metal layer n-2 (and / or see FIG. 12 if another metal layer is desired). This will be described in more detail. Additional evaluation lines are programmed by filling vias to connect, attach and connect them to the conductive pads. As will be apparent to those skilled in the art, the filling vias are formed as separate plugs, depending on the process used, between the formation of the metal layer n-2 and the metal layer n-1 or during the formation of the metal layer n-1.
    [52] In the embodiment shown in FIG. 7, only transistor pairs 213, 214, 215, and 216 are shown for convenience and some layers are omitted for clarity (eg, the high-dimensional metal layer is omitted on the left side of FIG. 7). . However, as shown in Figs. 8-12, a complete arrangement of transistors (in this embodiment, other conductive EHs are used as transistors of the type but referred to as NMOS transistors). For example, in a cross sectional view taken along line 8-8 of FIG. 8 with a pair of transistors 215, a semiconductor substrate 211 is provided, which is a doped p type in this embodiment. A plurality of switching transistor pairs 213, 214, 215, and 216 are formed in rows and columns on a substrate to form an array. Since each pair of switching transistors is substantially similar, only one pair 215 will be described in detail.
    [53] 7 and 8, it can be seen that the transistor 215 pair includes a common source terminal 220 having drain terminals 221 and 222 spaced from the source terminal 220. The gap forms a second channel region having a gate terminal 229 in an overlapping position with a first channel region 225 having a gate terminal 226 in an overlapping position. As shown in FIG. 7, another common source terminal of an adjacent pair of common source terminal 220 and switching transistors 213, 214, 215, and 216 is an address line 230 that is an extension of the common source region 220. Are connected to each other by A common source terminal is disclosed for each pair of switching transistors, but if necessary, the common electrode should connect the terminals to be a drain electrode. In addition, each gate terminal for each transistor in the transistor column is connected to an address line such as, for example, a line 231 connecting the gate terminal 226 and a line 232 connecting the gate terminal 229. Are connected to each other by These address lines 231, 232 preferably extend at right angles in FIG. 9, showing the gate terminals 226, 229. Lines 231 and 232 are formed of polysilicon in this embodiment, but may be formed and / or connected to a first metal layer if necessary. In addition, field oxide layer 235 or other insulating means such as trench isolation are located between and around adjacent drain electrodes to separate the pair of transistors and prevent the formation of parallel external current paths. Herein, a pair of transistors sharing a common terminal is described as a preferred embodiment, but if necessary for a particular application, each transistor has no shared terminal and / or does not have a common address line 231, 232 to be manufactured separately. Can be.
    [54] The plurality of conductive layers (1 to n-2 in this embodiment) are sequentially formed and connected. In general, such conductive layers are consistent with the conductive layers typically formed during the fabrication of associated integrated circuits and substantially comprise the number required by the associated integrated circuits. The plurality of conductive layers are connected to respective drains (eg, 221 and 222) of each pair of switching transistors 213, 214, 215, and 216, and are connected to each other by vias filled with an electrically conductive material. In Figures 8 and 11, the plurality of conductive layers is shown as a row 239 of metals located at each drain terminal and electrically connected. 10 and 11, a plurality of bit lines 240 are formed in the metal layer n-2 spaced apart from each other and spaced apart from the column 239. As shown in FIGS. Optionally, a gate strap 237 (not shown in FIG. 8) may be included, periodically connected to the address lines 231, 232 to the gate terminals 229, 226.
    [55] The final conductive layer (n-1 in this embodiment) of the plurality of conductive layers is deposited and formed to define the conductive pads 241 for each of the drain terminals and to contact the drain terminals through the connected rows 239. The conductive pad 241 has a somewhat thin and long structure to form a structure on the connected bit line 240 as shown in FIG. 11 (see FIG. 7). Fill via 242, that is, via filled with an electrically conductive material, is selectively formed between bit line 240 and selected conductive pad 241. As described below, the fill via 242 is formed between the formation of the metal layer n-2 and the metal layer n-1 or during the formation of the metal layer n-1, depending on the process used. In general, in this example, the inclusion of the fill via is labeled "0" and the omission of the filling via 242 is labeled "1".
    [56] In a similar manner, a pair of filling vias 243 and 244, ie, vias filled with an electrically conductive material, are selectively formed or not formed between the conductive pad 241 and the formation of the pair of bit lines 246 and 247. Do not. The bit lines 246 and 247 are formed in the metal layer n and the filling vias 243 and 244 are formed as separate plugs between the metal layers n and n-1 formation or the metal layer n or the metal layer n-1 depending on the process used. Formed as part. In this embodiment, the inclusion of the filling vias 243 and 244 is indicated by the output "0" in conjunction with the bitline 246 or 247, and the omission of the filling vias 243 and 244 is indicated by the bit line 246 or 247) and is indicated by the output " 1 ". In this embodiment, the programming portion of the ROM 210 is made during the formation of a plurality of metal layers (ie, contact layers to metal layer n-1), ie, filling vias 242. However, if only fill vias 243 and 244 are included, all programming takes place after the plurality of metal layers are formed. That is, all programming takes place only with the formation of fill vias 243 and 244 and bitlines 246 and 247.
    [57] In general, the bit lines 240, 246, 247, referred to as evaluation lines or signal lines, extend to the edge of a block of ROM 210 or to an array of switching transistors provided with external contacts or terminals. Therefore, three evaluation lines or signal lines or bit lines are arranged to be selectively connected to each cell (switching transistor) in each row of cells of ROM 210 by fill vias 242, 243 and 244. In addition, the gates (particularly gates 228, 229) of the pair of transistors 213, 214, 215, 216 are connected in columns by word or address lines 231, 232, and are formed of a material such as polysilicon. do. Each transistor in the transistor array has three bit lines and three potentially filled vias, providing two bits of data encoded by four different states. For ease of description of operation, bitline 246 is designated BL0, bitline 247 is designated BL1, and bitline 240 is designated BL2.
    [58] In a preferred method of operation of ROM 210, a common source or signal line for each pair of transistors (eg, source 220 for pair of transistors 215) is grounded through address line 230. Individual transistors in the transistor array can be addressed by supplying an activation potential to address lines 231 and 232 connected to the gates of the transistors to be addressed, and sequentially supplying "read" voltages to the bit lines BL0, BL1, BL2 to be read. When the bit line or signal line BL0 is activated or read out, if a fill via 243 is present, current will flow through the selected transistor as indicated by " 0 " in this embodiment. If there is no fill via 243, current will not flow through the selected transistor as indicated by " 1 " in this embodiment. Likewise, when each bit line or signal line BL1, BL2 is activated, " 0 " or " 1 " will be read, respectively, with or without filling vias 244,242.
    [59] In a preferred method of operation, a voltage or current sensing method is used to simultaneously sense bit lines BL0, BL1, BL2. In this encoding process, four states are generated for three evaluations or bitlines. The four states are shown in Table 1 below.
    [60] Table 1
    [61] BL0 BL1 BL2
    [62] State 0: 1 1 1 No filling vias
    [63] State 1: 0 1 1 Filling Vias (243)
    [64] State 2: 1 0 1 Filling Vias (244)
    [65] State 3: 1 1 0 Fill Via (242)
    [66] The four states represent 2-bit data. This is an encoding that allows the manufacture of large cells, or a small per bit due to the encoding. The more evaluations or bitlines, the more states can be encoded. An unprogrammed (without fill via) evaluation or bitline is in one state, and each fill via represents a different state. The more layers and metals are used in an integrated circuit (or ROM), the more the same density but the more bits are encoded. Additional bits allow the programming process to be first in the manufacturing process.
    [67] Including additional bit line 240 and optional fill via 242 may provide additional memory bits for each transistor of ROM 210 (ie, ROM 10 or 110 shown in FIGS. 1 and 4 respectively). On). The embodiment of FIG. 7 (ie ROM 210) has the advantage that almost half the chip or IC area per bit is required over ROM 10 or 110. The disadvantage is that the manufacturing process requires twice the programming steps. Also, the first programming step is carried out during the deposition of the initial metal layer, ie at the beginning of the manufacturing process specification. However, in many applications, the substantially reduced chip-per-bit area compensates for initial programming. In certain applications, it is convenient to include a larger number of evaluation lines in the initial metal layer to increase the number of memory bits that can be stored in each cell.
    [68] As can be seen in the various figures and embodiments described above, the main source of area savings in the new ROM is the use of three or more metal layers in a multilayer integrated circuit. In traditional ROM, the goal is to create as small as possible bit cells, scaling by the active region and the cell's programming mechanism.
    [69] A strapping composite sense amplifier is used to sense the current that becomes the source current or sink current of a conventional cell.
    [70] In the new ROM described here, no special cell has been fabricated because standard transistors can be used. Each new cell can provide two bits of data, so the device can effectively double the area. That is, the area per bit is cut in half so that each cell area is doubled and the module maintains the same size as the prior art ROM. Therefore, in the new ROM, it can be seen that the burden of developing a small cell is reduced compared to the presently disclosed technique or programming method.
    [71] In addition, due to the new ROM cell structure, the cell size is limited to metal and is not determined by the effective area. It is also possible to increase or decrease the size of the effective area of the cell in the new ROM while increasing / decreasing the speed capability of the current sink / source and device without affecting the array efficiency. This creates a simple sensing mechanism to achieve low power or high speed ROM, making circuit design easy and safe. Also, in other processes, the new ROM uses the NMOS or PMOS low voltage devices of the embodiments of the present invention, so there are no process instability or additional process costs. In addition, since the effective area is irrelevant to the size, the cell can be easily reapplied to other applications without changing the array efficiency.
    [72] Several embodiments and fabrication methods for ROM embedded in a multilayer integrated circuit have been disclosed. In some embodiments, programming is performed with final metal layer deposition and ROM is inactive. This ensures that the ROM maintains the standard until the final process step, so changes in the last few minutes of code have little impact on the customer's cycle time. In some embodiments, programming is performed with deposition of two or more metal layers, optimally the final metal layer, and the manufacturing process is slightly complicated but the chip area per bit is substantially reduced.
    [73] While specific embodiments of the invention have been shown and described, it will be apparent to those skilled in the art that further modifications and improvements are possible. Therefore, the invention is not limited to the specific forms shown above, but includes all modifications of the appended claims without departing from the spirit and scope of the invention. For example, ROM programming may be started at an earlier stage than the manufacturing process described in the embodiment of FIG. 11 by moving some of the programming to another layer as shown in FIG. It is also possible to increase the use of metal lines or layers and bit lines to increase the number of bits encoded per transistor.
    权利要求:
    Claims (9)
    [1" claim-type="Currently amended] In a read-only memory (ROM) embedded in a multilayer integrated circuit,
    A semiconductor substrate 11 having a plurality of switching transistors 12, 13, 14, 15, 16, 17, 18 formed in a first direction, wherein each switching transistor of the plurality of switching transistors acts as a memory cell and is formed of the first substrate. A plurality of switching transistors in one direction, said semiconductor substrate (11) defining a row of memory cells;
    A plurality of first signal lines 36, 37, 38, 39 connected to the plurality of switching transistors, each of the first signal lines of the plurality of first signal lines being associated with a corresponding switching transistor of the plurality of switching transistors; A plurality of first signal lines connected to a first terminal, each of the first signal lines of the plurality of first signal lines serving as one contact terminal for at least one memory cell in the row of memory cells; 36, 37, 38, 39);
    A plurality of conductive layers connected to a second terminal of each associated switching transistor of the plurality of switching transistors and connected to each other by a filling via 60, and defining a plurality of conductive pads 45, 46, 47, and 48; A plurality of conductive layers, each conductive pad being connected to an associated second terminal of a corresponding switching transistor of the plurality of switching transistors;
    A plurality of second signal lines 52, 53 serving as output terminals for a row of memory cells;
    Additional fill vias connecting selected pads of the conductive pads to selected lines of the second plurality of signal lines, the second plurality of signal lines acting as output lines of the row of memory cells Read only memory (ROM) embedded in a multilayer integrated circuit, including vias.
    [2" claim-type="Currently amended] The method of claim 1,
    Each transistor in the row of memory cells shares a common terminal 31, 28 with an adjacent transistor in the row of memory cells, such that adjacent pairs of transistors in the row of memory cells have a source terminal 31 and a drain terminal 28. Wherein the plurality of first signal lines are each connected to respective common terminals, wherein each of the plurality of first signal lines is embedded in a multilayer integrated circuit.
    [3" claim-type="Currently amended] The method of claim 1,
    And each switching transistor in said plurality of switching transistor rows is arranged to form a plurality of switching transistor columns.
    [4" claim-type="Currently amended] The method of claim 3, wherein
    Each switching transistor of the plurality of switching transistor rows and the plurality of switching transistor columns comprises a gate terminal 226, each column of switching transistors having all gate terminals of the switching transistors in a column connected together. Built-in read-only memory (ROM).
    [5" claim-type="Currently amended] The method of claim 3, wherein
    Each of the plurality of second signal lines is oriented generally parallel to the rows of the switching transistors, each row of switching transistors having an associated pair of second signal lines.
    [6" claim-type="Currently amended] The method of claim 1,
    The plurality of conductive layers connected to the second terminals and connected to each other by conductive filling vias further include a plurality of third signal lines in the first conductive layer before the conductive layer, wherein the filling via is conductive Read-only memory (ROM) embedded in a multilayer integrated circuit that connects selected pads of pads to select lines of the plurality of third signal lines.
    [7" claim-type="Currently amended] The method of claim 1,
    And the plurality of first signal lines are made of the associated first terminals, each of the first signal lines including a contact adjacent an edge of a memory block.
    [8" claim-type="Currently amended] The method of claim 1,
    And the plurality of first signal lines comprises a doped semiconductor material.
    [9" claim-type="Currently amended] The method of claim 1,
    And the plurality of conductive layers and filling vias comprise a metal.
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    同族专利:
    公开号 | 公开日
    JP2003534663A|2003-11-18|
    WO2001091185A3|2002-03-28|
    AU5154901A|2001-12-03|
    KR100794482B1|2008-01-16|
    TW507204B|2002-10-21|
    CN1437767A|2003-08-20|
    US6498066B2|2002-12-24|
    US20020042182A1|2002-04-11|
    WO2001091185A2|2001-11-29|
    CN1262015C|2006-06-28|
    JP4873819B2|2012-02-08|
    US6355550B1|2002-03-12|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2000-05-19|Priority to US09/575846
    2000-05-19|Priority to US09/575,846
    2001-04-11|Application filed by 모토로라 인코포레이티드
    2002-12-31|Publication of KR20020097486A
    2008-01-16|Application granted
    2008-01-16|Publication of KR100794482B1
    优先权:
    申请号 | 申请日 | 专利标题
    US09/575846|2000-05-19|
    US09/575,846|US6355550B1|2000-05-19|2000-05-19|Ultra-late programming ROM and method of manufacture|
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